Dual-Phase, Quick-PWM Controller
for IMVP6+ CPU Core Power Supplies
I L ?
C OUT
η TOTAL
× ( dV TARGET / dt )
remains blanked high impedance until 20μs after the
output voltage reaches the internal target. Once this
time expires, PWRGD monitors only the lower threshold.
where dV TARGET /dt is the required slew rate, C OUT is
the total output capacitance, and η TOTAL is the number
of active phases.
Deeper Sleep Transitions
When DPRSLPVR goes high, the MAX17410 immediate-
ly disables phase 2 (DH2 and DL2 forced low), blanks
PHASEGD high impedance, and enters pulse-skipping
operation (see Figures 4 and 5). If the VIDs are set to a
lower voltage setting, the output drops at a rate deter-
mined by the load and the output capacitance. The
internal target still ramps as before, and PWRGD
ACTUAL V OUT
CPU CORE VOLTAGE
INTERNAL TARGET
Fast C4E Deeper Sleep Exit: When exiting deeper
sleep (DPRSLPVR pulled low) while the output voltage
still exceeds the deeper sleep voltage, the MAX17410
quickly slews (50mV/μs min regardless of R TIME setting)
the internal target voltage to the DAC code provided by
the processor as long as the output voltage is above
the new target. The controller remains in skip mode
until the output voltage equals the internal target. Once
the internal target reaches the output voltage, phase 2
is enabled. The controller blanks PWRGD, PHASEGD,
and CLKEN (forced high impedance) until 20μs after
the transition is completed. See Figure 4.
VID (D0-D6)
DPRSLPVR
DPRSTP
PSI
DEEPER SLEEP VID
DO NOT CARE (DPRSLPVR DOMINATES STATE)
INTERNAL
PWM CONTROL
DH1
DH2
1-PHASE SKIP (DH1 ACTIVE, DH2 = DL2 = FORCED LOW)
NO PULSES: V OUT > V TARGET
FORCED PWM
PWRGD
CLKEN
PHASEGD
OVP
BLANK HIGH-Z
BLANK LOW
BLANK HIGH THRESHOLD ONLY
BLANK HIGH THRESHOLD ONLY
BLANK HI-Z (1-PHASE OPERATION)
SET TO 1.75V MIN
BLANK HI-Z
BLANK LOW
TRACKS INTERNAL TARGET
Figure 4. C4E (C4 Early Exit) Transition
t BLANK
20 μ s TYP
t BLANK
20 μ s TYP
______________________________________________________________________________________
31
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